(1) Field of the Invention
The present invention relates to a non-volatile memory cell using a ferroelectric capacitor, and a method of controlling the same.
(2) Description of the Related Art
In recent years, the widespread use of portable devices has been driving the demand for non-volatile memories. Non-volatile memories which have been developed or suggested until now include flash memories, those called FERAMs utilizing the polarization of ferroelectric substances, those called MRAMs utilizing magnetic resistance, and those utilizing phase change materials, etc.
Especially, many non-volatile memory cells using ferroelectric capacitors have been suggested, and memory cells having a high-speed latch function and a non-volatile memory function have been also suggested. For example, there is a circuit which is generally called a shadow RAM and disclosed in the Japanese Patent No. 2692641 (hereinafter referred to as “reference 1”) and Japanese Unexamined Patent Publication No. 2000-293989 (hereinafter referred to as “reference 2”).
The circuit diagram of the shadow RAM disclosed in reference 1 is shown in FIG. 10. The circuit shown in FIG. 10 is configured to comprise a data latch section consisting of a pair of inverters, a pair of data lines, a control line, a pair of control transistors connected between the data lines and control line and a pair of ferroelectric capacitors connected between the data lines and the control line. The circuit of FIG. 10 usually operates in a similar manner to a flip-flop using the data lines. In order to achieve non-volatility, however, it operates in a different manner from a normal flip-flop. Specifically, the circuit controls the potential of the control line and saves data as the polarization states of the ferroelectric capacitors immediately before power is removed (hereinafter referred to as “STORE”). When power is turned on, the original data is recalled depending on the polarization states of the ferroelectric capacitors (hereinafter referred to as “RECALL”).
The circuit diagram of the shadow RAM disclosed in reference 2 is shown in FIG. 11. This circuit is configured to comprise a data latch section consisting of a pair of inverters, a pair of bit lines, a plate line, a pair of control transistors which connect the bit lines to the data latch section, a pair of ferroelectric capacitors connected between the data latch section and the plate line. Select transistors which select a cell in the shadow RAM are omitted in FIG. 11. The circuit turns on the select transistors and writes data during normal operation. Similarly, latched data is read by turning on the select transistors. In contrast, the STORE of data when power is removed is different from the normal flip-flop operation, the data in the latch section is written into the ferroelectric capacitors using the plate line. Also in the RECALL when power is turned on, the original data is recalled by controlling the potential of the plate line.
However, the above known non-volatile memory cells have the following problems:
In the circuits of FIGS. 10 and 11, in the STORE, unlike in the flip-flop operation, the data of the latch section is written into the ferroelectric capacitors using the control line or plate line. That is, in order to control the polarization reversal operation of the ferroelectric capacitor, at least another signal line such as the control line or plate line is necessary. Accordingly, a control signal for the signal line must be transmitted to the memory cell using an additional line. These circuits, therefore, need to have additional control lines and plate lines, which increases the number of electric wires. This disadvantage has been preventing the circuits from being used for FPGAs, which have a large number of electric wires by themselves.
In normal flip-flop operation, to prevent voltage application to the ferroelectric capacitors, the potential approximately half the height of the supply voltage is applied to the plate line. However, a ferroelectric capacitor shows a minor loop which indicates that a certain degree of polarization is caused with the application of a voltage, even if it is lower than the coercive electric field. Therefore, the potentials of the storage nodes of the data latch section become easily displaced by the minor loop of the ferroelectric capacitors. Therefore, the relationship between the capacitance of the ferroelectric capacitor and the drive ability of the inverter which constitutes the data latch section must be set appropriately. However, it is difficult to design this relationship appropriately. As a result, the retained potential becomes unstable during normal latch operation, and there arises the problem of being unable to keep the operation stable.
Furthermore, although the relationship between the coercive electric field and the electric field of a polarization saturation point varies with ferroelectric substance materials, many kinds of ferroelectric capacitors usually have the electric field of a polarization saturation point twice as high as the coercive electric field or higher. Therefore, it is difficult to cause the saturation polarization of a ferroelectric capacitor unless the potential of a plate line is biased to a level equal to or higher than the ground potential or supply potential. For this reason, the capacitor would need to use a special booster circuit. Otherwise, even if a voltage about half the height of the supply voltage is preliminarily applied to the plate line, only an electric field twice as high as a normal electric field, at the highest, could be applied to the ferroelectric capacitor. That is, when a voltage about half the height of the supply voltage is applied to the plate line, an electric field equal to or lower than the coercive electric field is desirably applied to the ferroelectric capacitor. Considering this, even if the potential of the plate line is changed to the supply potential or the ground potential, it would be difficult to apply an electric field which causes the polarization saturation of the ferroelectric substance to the ferroelectric capacitor.